1. Field of the Invention
The present invention relates to a semiconductor memory device where word lines are divided into sub word lines.
2. Description of the Related Art
As semiconductor memory devices such as dynamic random access memory (DRAM) devices have been highly integrated, the number of memory cells connected to one word line has been increased, which increases the load of the word line.
In a prior art DRAM device, in order to decrease the load of word lines, each of the word lines are divided into a plurality of sub word lines. In other words, a plurality of sub word lines are under one main word line. This will be explained later in detail.
Even in the prior art device, when the number of memory cells connected to one sub word line is increased, the length of the sub word line is increased so that the load thereof is increased. As a result, rising and falling of the voltage at the terminal of the sub word line opposite to a corresponding sub word line drive circuit is remarkably delayed, which decreases the access speed.
In order to increase the access speed, an additional reset transistor may be connected to the terminal of the sub word line (see JP-A-60-167193). In this case, however, the connections for the additional reset transistors are required, which increases the chip area and decreases the integration.